------------------------------------------------------------------------------- -- Project : stoch_add -- File : stoch_lib.vhdl -- Desc : Package for stochastic components in the library ------------------------------------------------------------------------------- -- Authors : Ardalan Najafi -- Company : ITEM -- Created : 2016-09-28 -- Last update : 2016-09-28 ------------------------------------------------------------------------------- -- Copyright (c) 2016 ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2016-08-28 1.0 agarcia Created ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; use work.pkg_add.all; package stoch_lib is type ppType is (SK, BK, KS); component PrefixAndOr_SK generic (B : positive); -- word width port ( pg_i : in pg_vec(B-1 downto 0); -- gen./prop. in pg_o : out pg_vec(B-1 downto 0)); -- gen./prop. out end component; component PrefixAndOr_LF generic (B : positive); -- word width port ( pg_i : in pg_vec(B-1 downto 0); -- gen./prop. in pg_o : out pg_vec(B-1 downto 0)); -- gen./prop. out end component; component PrefixAndOr_BK generic (B : positive); -- word width port ( pg_i : in pg_vec(B-1 downto 0); -- gen./prop. in pg_o : out pg_vec(B-1 downto 0)); -- gen./prop. out end component; component PrefixAndOr_KS generic (B : positive); -- word width port ( pg_i : in pg_vec(B-1 downto 0); -- gen./prop. in pg_o : out pg_vec(B-1 downto 0)); -- gen./prop. out end component; component x port ( a, b : in std_logic; s : out std_logic); end component; component pg port ( a, b : in std_logic; p, g : out std_logic); end component; component c_ser port ( pg_i : in pg_vec; pg_o : out pg_vec); end component; component c_lev port ( pg_l : in pg_t; pg_i : in pg_vec; pg_o : out pg_vec); end component; component c2 port ( pg_m, pg_l : in pg_t; pg_o : out pg_t); end component; component mux_nb generic (B : natural); port ( da, db : in std_logic_vector(B-1 downto 0); sel : in std_logic; do : out std_logic_vector(B-1 downto 0)); end component; component fau port ( a, b, ci : in std_logic; s, co : out std_logic); end component; --------------------------------------------------------------- --------------------------Adders------------------------------- --------------------------------------------------------------- component add_exact generic ( BW : natural := 16); port ( in1, in2 : in std_logic_vector(BW-1 downto 0); res : out std_logic_vector(BW downto 0)); end component; component add_rc generic (B : natural); port ( ci : in std_logic; da, db : in std_logic_vector(B-1 downto 0); do : out std_logic_vector(B-1 downto 0); co : out std_logic); end component; component adder generic (B : natural); port ( ci : in std_logic; da, db : in std_logic_vector(B-1 downto 0); do : out std_logic_vector(B-1 downto 0); co : out std_logic); end component; component adder1 generic (B : natural); port ( da, db : in std_logic_vector(B-1 downto 0); do : out std_logic_vector(B-1 downto 0); co : out std_logic); end component; component add_rc2 generic (B : natural); port ( ci : in std_logic; da, db : in std_logic_vector(B-1 downto 0); do : out std_logic_vector(B-1 downto 0); co : out std_logic); end component; component add_pp_SK generic (B : natural); port ( ci : in std_logic; da, db : in std_logic_vector(B-1 downto 0); do : out std_logic_vector(B-1 downto 0); co : out std_logic); end component; component add_pp_BK generic (B : natural); port ( ci : in std_logic; da, db : in std_logic_vector(B-1 downto 0); do : out std_logic_vector(B-1 downto 0); co : out std_logic); end component; component add_pp_KS generic (B : natural); port ( ci : in std_logic; da, db : in std_logic_vector(B-1 downto 0); do : out std_logic_vector(B-1 downto 0); co : out std_logic); end component; component add_csa generic (B : natural; ks : blk_def_t); port ( ci : in std_logic; da, db : in std_logic_vector(B-1 downto 0); do : out std_logic_vector(B-1 downto 0); co : out std_logic); end component; component add_eta2 generic (B : natural; ks : blk_def_t); port ( ci : in std_logic; da, db : in std_logic_vector(B-1 downto 0); do : out std_logic_vector(B-1 downto 0); co : out std_logic); end component; component add_segmented generic (B : natural; kc : blk_def_t; ks : blk_def_t); port ( ci : in std_logic; da, db : in std_logic_vector(B-1 downto 0); do : out std_logic_vector(B-1 downto 0); co : out std_logic); end component; component add_eta2_sk generic (B : natural; ks : blk_def_t); port ( ci : in std_logic; da, db : in std_logic_vector(B-1 downto 0); do : out std_logic_vector(B-1 downto 0); co : out std_logic); end component; component add_esa generic (B : natural; ks : blk_def_t); port ( ci : in std_logic; da, db : in std_logic_vector(B-1 downto 0); do : out std_logic_vector(B-1 downto 0); co : out std_logic); end component; component add_loa generic (B : natural; ks : blk_def_t); port ( ci : in std_logic; da, db : in std_logic_vector(B-1 downto 0); do : out std_logic_vector(B-1 downto 0); co : out std_logic); end component; ---------------------------------------------------------------------- ---------------------------------------------------------------------- end stoch_lib;